mitsubishi electric 1997-5-28d.rev mitsubishi M62398P,fp 8bit 12ch i c bus d? converter with buffer amplifiers ( / 7) 2 general description the M62398P,fp is a 12v type cmos 12-channel d? converters with output buffer amplifiers. it can communicate with a microcontroller via few wiring thanks to the adoption of the two-line i 2 c bus. the output buffer amplifier employs ab class output with sinking and sourcing capability of more than 2.5ma ,and an output voltage range is nearly between ground and vrefu. maximum 8 ics can be connected to a bus by using three chip-set pins , so that it is possible to handle up to 96 channels. features ?wide output range nearly between ground and vrefu(0~12v). ?high output current drive capability over ?.5ma ?2 setting voltage ranges by dual input pins for upper voltage references (vref u1,u2 ) application conversion from digital control data to analog control data for both consumer and industrial equipment. gain control and automatic adjustment of display-monitor or ctv. ?i 2 c bus serial data method block diagram outline M62398P,fp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 r scl sda vrefl ao7 ao8 ao9 ao10 gnd vrefu1 cs0 cs1 cs2 v dd ao6 ao5 ao4 ao3 v cc vrefu2 21 22 23 24 ao11 ao12 ao2 ao1 pin configuration (top view) 24p4d (p) 24p2n-b (fp) 1 r1 r2 r1 r2 r1 r2 r1 r2 r1 r2 r1 r2 r2 r1 =2.4 chip select 8bit latch 8bit upper segment r-2r 8bit latch 8bit upper segment r-2r i 2 c bus transceiver address decoder 8 8bit latch 8bit upper segment r-2r 8bit latch 8bit upper segment r-2r 8bit latch 8bit upper segment r-2r 8bit latch 8bit upper segment r-2r 8bit latch 8bit upper segment r-2r 8bit latch 8bit upper segment r-2r 8bit latch 8bit upper segment r-2r 8bit latch 8bit upper segment r-2r 8bit latch 8bit upper segment r-2r scl sda v refl ao7 ao8 ao9 ao10 ao11 ao12 gnd v refu1 v refu2 v cc ao1 ao2 ao3 ao4 ao5 ao6 v dd cs2 cs1 cs0 8bit latch 8bit upper segment r-2r r1 r2 r1 r2 r1 r2 r1 r2 r1 r2 r1 r2 r 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
mitsubishi electric 1997-5-28d.rev mitsubishi M62398P,fp 8bit 12ch i c bus d? converter with buffer amplifiers ( / 7) 2 explanation of terminals 2 pin no. symbol 3 1 2 serial data input terminal reset signal input terminal serial clock input terminal 19 4 5 18 8bit d? converter output terminal f u n c t i o n 14 15 16 17 13 20 analog power supply terminal digital power supply terminal analog and digital common gnd d? converter low level reference voltage input terminal d? converter high level reference voltage input terminal 1 d? converter high level reference voltage input terminal 2 21 12 10 11 22 23 24 chip select data input terminal 2 chip select data input terminal 1 chip select data input terminal 0 sda r scl ao1 ao2 ao3 ao4 ao5 ao6 ao7 ao8 v cc v dd gnd vrefl vrefu1 vrefu2 cs2 cs1 cs0 ao9 ao10 ao11 ao12 6 7 8 9
mitsubishi electric 1997-5-28d.rev mitsubishi M62398P,fp 8bit 12ch i c bus d? converter with buffer amplifiers ( / 7) 2 absolute maximum ratings electric characteristics (v cc =13v,v dd =vref u1,2=+5v?0%,gnd=vrefl=0v,ta=?0~85?,unless otherwise noted) digital part < > symbol v dd supply voltage i ilk input leak current v il input low voltage v ih input high voltage parameter test conditions v in =0~v dd ratings min typ max 0.8v dd ?0 10 0.2v dd unit v v v i dd supply current ma clk=1mhz operation i ao =0? 4.5 5.0 5.5 ?a 1 analog part < > (v cc =13v,v dd =vrefu1,2=+5v?0%,gnd=vrefl=0v,ta=?0~85?,unless otherwise noted) supply voltage clk=1mhz operation i ao =0? supply current 13 v ma symbol parameter test conditions ratings min typ max unit d? converter upper reference voltage input current vrefu=5v,vrefl=0v data condition: at maximum current ma d? converter upper reference voltage range the output dose not necessarily be the values within the reference voltage setting range. d? converter lower reference voltage range buffer amplifier output voltage range i ao =?00? i ao =?.0ma 3.5 v gnd 1.5 v 0.1 v cc -0.1 v 0.2 v buffer amplifier output drive range upper side saturation voltage=0.3v lower side saturation voltage=0.2v ?.5 2.5 ma v cc i cc irefu vrefu vrefl v ao i ao s dl s l s zero s full sr differential nonlinearity error nonlinearity error zero code error full scale error vrefu=4.79v vrefl=0.95v v cc =13v(36mv/lsb) without load (i ao =0) ?.0 1.0 ?.5 1.5 ?.0 2.0 ?.0 2.0 0.2 lsb lsb lsb lsb 2.4v dd 2.0 4.0 1.2 2.5 v dd output slew rate v/? v cc -0.2 3 symbol v cc v dd vrefu1,2 vin d pd topr tstg supply voltage supply voltage d? converter upper reference voltage digital input voltage power dissipation operating temperature storage temperature parameter conditions ?.3~13.5 ?.3~7.0 ?.3~v dd +0.3 ?0~85 ?0~125 unit v v v v mw ratings ? 465(dip) /421(fp) v dd ?
mitsubishi electric 1997-5-28d.rev mitsubishi M62398P,fp 8bit 12ch i c bus d? converter with buffer amplifiers ( / 7) 2 4 i2c bus line characteristics scl clock frequency time the bus must be free before a new transmission can start f scl t buf t hd:sta t low t high t su:sta t hd:dat t su:dat t r t f t su:sto khz ? ns ns ns min. 0 4.7 4.0 4.7 4.0 4.7 0 250 4.0 - - max. 100 1000 300 - - - - - - - - min. 0 1.3 0.6 1.3 0.6 4.7 0 100 0.6 20+ 20+ max. 400 300 300 - - - - - 0.9 - - parameter hold time start condition. after this period,the first clock pulse is generated. low period of the clock high period of the clock set-up time for start condition (only relevant for a repeated start condition) hold time data set-up time data rise time of both sda and scl lines fall time of both sda and scl lines set-up time for stop condition *note that a transmitter must internally provide at least a hold time to bridge the undefined region (max.300 ns) of the falling edge of scl. symbol normal mode high speed mode units timing chart ? ? ? ? ? ? t r, t f t buf t low t high t hd:dat t su:dat sda scl v ih v il v ih v il t hd:sta t su:sta t su:sto start start stop start
mitsubishi electric 1997-5-28d.rev mitsubishi M62398P,fp 8bit 12ch i c bus d? converter with buffer amplifiers ( / 7) 2 5 i c- bus format 2 digital data format ?lave address first last chip select data (slave address) ?ac data first msb last lsb ?ub address channel select data don't care last first sta slave address w a sub address a dac data a stp 1 0 0 1 a2 a1 a0 d2 d1 d0 d3 d4 d5 d6 d7 x x x s2 s1 s0 s3 x (1)chip select data msb lsb (3)dac data msb lsb first last a2 0 0 1 0 a1 0 0 1 1 a0 1 0 0 1 0 0 0 1 cs2 0 0 1 1 cs1 0 1 0 1 cs0 lower 3bits(a0,a1,a2) are a programmable address. this ic is accessed only when the lower 3 bits data of slave address coincide with the data of cs0 to cs2.(refer to the upper table) d6 0 0 0 0 1 1 dac output (v ref u -v ref l )/256 x 1 x 2.4 + v ref l (v ref u -v ref l )/256 x 2 x 2.4 + v ref l (v ref u -v ref l )/256 x 3 x 2.4 + v ref l (v ref u -v ref l )/256 x 4 x 2.4 + v ref l (v ref u -v ref l )/256 x 255 x 2.4 + v ref l (v ref u -v ref l ) x 2.4 + v ref l d7 0 0 0 0 1 1 d5 0 0 0 0 1 1 d4 0 0 0 0 1 1 d3 0 0 0 0 1 1 d2 0 0 0 0 1 1 d1 0 0 1 1 1 1 d0 0 1 0 1 0 1 (2)channel select data msb lsb s0 0 1 0 1 0 1 1 s1 0 0 1 1 0 1 0 s2 0 0 0 0 1 1 1 s3 0 0 0 1 1 1 1 don't care. don't care. don't care. ch1 selection ch2 selection ch11 selection ch12 selection channel selection
mitsubishi electric 1997-5-28d.rev mitsubishi M62398P,fp 8bit 12ch i c bus d? converter with buffer amplifiers ( / 7) 2 6 timing chart (model) ?tart condition ?with scl at high,sda line goes from high to low ?top condition ?with scl at high,sda line goes from low to high (*under normal circumstances,sda is changed when scl is low) ?cknowledge bit the receiving ic has to pull down sda line whenever receive slave data. (the transmitting ic releases the sda line just then transmit 8bit data.) ?ac data bite to stop condition sda scl r dac output 1 2 a 3 4 5 6 7 w ?tart condition to slave address bite start condition stop condition sda scl r dac output 1 2 a 3 4 5 6 7 8 ?ub address bite sda scl r dac output 1 2 a 3 4 5 6 7 8
mitsubishi electric 1997-5-28d.rev mitsubishi M62398P,fp 8bit 12ch i c bus d? converter with buffer amplifiers ( / 7) 2 precaution for use m62398 have 5 terminals ( vdd,vcc,vrefu1,vrefu2,vrefl ) for input constant voltage at use. if ripple or spike is input these terminals,accuracy of d-a conversion is down. so,when use this device,please connect capacitor among each terminal to gnd for stable d-a conversion. this ic's output amplifier has an advantage to capacitive load.so it's no problem at device action when connect capacitor ( 0.1 f max ) among output to gnd for every noise eliminate. *purchase of mitsubishi electric corporation's i 2 c components conveys a license under the philips i 2 c patent rights to use these components an i 2 c system,provided that the system conforms to i 2 c standard specification as defined by philips. ao5 ch5 gnd vrefl vdd vcc ao1 ch1 ao4 ch4 ao6 ch6 ao8 ch8 ao9 ch9 ao10 ch10 ao12 ch12 10? vrefu1 vrefu2 10? 10? 10? ao2 ch2 ao3 ch3 ao7 ch7 ao11 ch11 sda scl mcu 5v 5v 5v 5v cs0 cs1 cs2 r 13v analog output terminals mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury,fire or property damage.remember to give due consideration to safety when making your circuit design,in order to prevent fires from spreading,redundancy,malfunction or other mishap. ! 7 10? chip select data setting reset signal
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